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ASIC Design Verification Engineer Interview Experience - San Jose, California

March 14, 2024
Positive ExperienceNo Offer

Process

The interviewer started with basics and built on them. Questions covered SV assertions, fork-join, swap, Fibonacci series, and recursive functions. Prepare your resume thoroughly. I was asked to describe my experience in detail.

Questions

SystemVerilog and C based questions

Fork join, assertions, coverage

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Interview Statistics

The following metrics were computed from 1 interview experience for the Juniper Networks ASIC Design Verification Engineer role in San Jose, California.

Success Rate

0%
Pass Rate

Juniper Networks's interview process for their ASIC Design Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Juniper Networks's ASIC Design Verification Engineer interview process in San Jose, California.

Juniper Networks Work Experiences