The interviewer started with basics and built on them. Questions covered SV assertions, fork-join, swap, Fibonacci series, and recursive functions. Prepare your resume thoroughly. I was asked to describe my experience in detail.
SystemVerilog and C based questions
Fork join, assertions, coverage
The following metrics were computed from 1 interview experience for the Juniper Networks ASIC Design Verification Engineer role in San Jose, California.
Juniper Networks's interview process for their ASIC Design Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Juniper Networks's ASIC Design Verification Engineer interview process in San Jose, California.