Senior ASIC Design Verification Engineer
Description For Senior ASIC Design Verification Engineer
Cisco's Common Hardware Group (CHG) is seeking a Senior ASIC Design Verification Engineer to join their team developing silicon solutions for networking hardware. This role focuses on verifying complex ASICs for high-end switching products, working with cutting-edge technology in Cisco Silicon One architecture. The position offers the opportunity to work with outstanding talent in ASIC development, collaborating with micro-architects, front-end designers, and system teams.
The role involves developing simulation models, test plans, and performing various verification tasks for ASIC designs. You'll be working with System Verilog/UVM and utilizing your expertise in ASIC design verification processes. The position requires strong technical skills and the ability to work collaboratively with cross-functional teams.
Cisco offers a comprehensive benefits package including medical, dental, vision insurance, 401k with company match, and various time-off benefits. The company culture promotes diversity and inclusion, with opportunities for professional growth and community involvement. The position is based in San Jose, California, at the heart of Silicon Valley, offering competitive compensation between $149,600 - $214,100 USD.
This is an excellent opportunity for experienced verification engineers looking to work on innovative networking hardware solutions at a global technology leader. The role combines technical challenges with the chance to impact the future of networking infrastructure while working with industry-leading professionals in a collaborative environment.
Responsibilities For Senior ASIC Design Verification Engineer
- Participate in ASIC design verification for Cisco high-end switching products
- Development of simulation models, test plans, direct and random tests
- Code or functional coverage, multi-chip/system simulation, and performance analysis
- Collaborate with hardware, software designers, and vendors
Requirements For Senior ASIC Design Verification Engineer
- Bachelor's degree in electrical or computer science or computer engineering with 7 years of related experience or Master's with 5 years experience
- Experience in System Verilog/UVM
- Experience with ASIC design and verification processes, debugging, methodology, and tools
- Experience in verifying blocks/clusters/full chip level for ASIC
Benefits For Senior ASIC Design Verification Engineer
- Medical insurance
- Dental insurance
- Vision insurance
- 401k with company match
- Short and long-term disability coverage
- Basic life insurance
- Paid holidays
- Vacation time
- Sick time off
- Volunteer time off
