Design Verification Engineer, Multimedia

Google is a global technology company that specializes in internet-related services and products, including search, cloud computing, software, and hardware.
$127,000 - $187,000
Backend
Mid-Level Software Engineer
Hybrid
5,000+ Employees
3+ years of experience
AI

Description For Design Verification Engineer, Multimedia

Google is seeking a Design Verification Engineer for their Multimedia team to contribute to the development of custom silicon solutions for direct-to-consumer products. The role involves planning and executing verification of complex Multimedia Hardware IPs at subsystem and full chip levels, creating constrained-random verification environments, and ensuring functionally correct design blocks.

As part of Google's mission to organize the world's information and make it universally accessible and useful, you'll be working on a team that combines AI, Software, and Hardware to create innovative hardware experiences. This role offers the opportunity to shape the next generation of hardware, delivering unparalleled performance, efficiency, and integration.

Key responsibilities include: • Planning verification of complex Multimedia HW IPs • Creating and enhancing verification environments using SystemVerilog and UVM • Identifying and writing coverage measures for stimulus and corner-cases • Debugging tests with design engineers • Closing coverage measures to ensure progress towards tape-out

The ideal candidate will have a strong background in electrical engineering or computer science, with experience in verification methodologies, digital logic verification, and object-oriented programming. Preferred qualifications include experience with formal verification techniques, multimedia IPs, and machine learning IPs.

This position offers a competitive salary range of $127,000-$187,000, plus bonus, equity, and benefits. Google is committed to creating a diverse and inclusive work environment, providing equal opportunities regardless of background.

Join Google's hardware team and contribute to developing innovative products that are used and loved by millions worldwide.

Last updated 18 days ago

Responsibilities For Design Verification Engineer, Multimedia

  • Plan the verification of complex Multimedia HW IPs at Subsystem and full chip level
  • Create and enhance constrained-random verification environments using System Verilog and UVM
  • Identify and write all types of coverage measures for stimulus and corner-cases
  • Debug tests with design engineers to deliver functionally correct design blocks
  • Close coverage measures to identify verification holes and to show progress towards tape-out

Requirements For Design Verification Engineer, Multimedia

Java
Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • 3 years of experience with verification methodologies and languages such as UVM and SystemVerilog
  • Experience verifying digital logic at Register-Transfer Level (RTL) using SystemVerilog for ASICs
  • Experience with object oriented programming

Benefits For Design Verification Engineer, Multimedia

Medical Insurance
Equity
  • Bonus
  • Equity
  • Health benefits

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