Google is seeking a Full Chip CAD Physical Design Verification Engineer to join their Technical Infrastructure team. This role involves developing custom silicon solutions for Google's direct-to-consumer products, contributing to the innovation behind products used by millions worldwide. The ideal candidate will have expertise in Electronic Design Automation (EDA) tools, RTL2GDS flows, and experience in the semiconductor/EDA industry.
Key responsibilities include working with Register-Transfer Level (RTL)-to-Graphic Data Stream (GDS)II flow, implementing complex system-on-chips (SoCs), and utilizing advanced floorplanning and power grid design methodologies. The role requires proficiency in using Cadence design tools and Synopsis tools like Floorplan Compiler (FC) and formality.
The position offers the opportunity to shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration. Candidates should have a strong background in electrical engineering or computer science, with experience in advanced node design (5nm and below) and related optimization techniques. Scripting skills in Synopsis TCL and Python are also essential.
Google emphasizes its commitment to diversity, equality, and inclusion, providing an equal opportunity workplace for all qualified candidates. The company offers accommodation for applicants with special needs and values global collaboration, requiring English proficiency for all roles unless stated otherwise.