Google is seeking a Principal Interposer Physical Design Engineer to join their Technical Infrastructure team. This role is crucial in developing custom silicon solutions that power Google's direct-to-consumer products. The position requires extensive experience in ASIC physical design and advanced process nodes, with a focus on interposer routing for 2.5D and 3D packaging.
The ideal candidate will have a strong background in electrical engineering or related fields, with at least 10 years of experience in ASIC physical design. They will be responsible for complex technical tasks including interposer routing, signal integrity analysis, and collaboration with various design teams.
Working at Google's Technical Infrastructure team means being part of the backbone that keeps Google's vast product portfolio running smoothly. The team is responsible for developing and maintaining data centers and building next-generation Google platforms. They take pride in being the "engineers' engineers" and are passionate about pushing technological boundaries.
This role offers an excellent compensation package, including a competitive base salary range of $177,000-$266,000, plus bonus, equity, and comprehensive benefits. The position is based in Sunnyvale, CA, offering the opportunity to work with cutting-edge technology and collaborate with some of the industry's best minds.
The successful candidate will contribute to innovative hardware solutions that impact millions of users worldwide. They will work on challenging technical problems, from custom signal routing to power/ground distribution, while considering high-speed effects and signal integrity. The role requires both technical expertise and collaborative skills, as they will work closely with ASIC designers, package designers, and system architects.
Google offers a supportive and inclusive work environment, with a strong commitment to diversity and equal opportunity. They provide comprehensive benefits and support for professional growth. This is an excellent opportunity for an experienced engineer looking to make a significant impact in the field of silicon design and contribute to Google's next generation of hardware experiences.