Network Design Engineer, Google Cloud
Description For Network Design Engineer, Google Cloud
Google is seeking a Network Design Engineer for their Cloud division to join their Technical Infrastructure team. This role involves developing custom silicon solutions and ASICs to accelerate networking in data centers. The position requires extensive experience in networking ASIC architecture, from specification to production. You'll be working on cutting-edge technology that powers Google's direct-to-consumer products, contributing to project definition, design, and implementation of next-generation data center accelerators. The role demands expertise in RDMA-based transports and deep understanding of networking protocols. As part of Google's Technical Infrastructure team, you'll help maintain and develop data centers, ensuring optimal network performance and user experience. The position offers the opportunity to work on groundbreaking data center networks and collaborate with software teams to optimize hardware/software interfaces.
Responsibilities For Network Design Engineer, Google Cloud
- Participate in evaluation of future ASIC designs and general architecture for executing Google's data center networking roadmap
- Collaborate in developing new layer protocols for data center networking
- Understand how it interacts with software and other ASIC subsystems to implement groundbreaking data center networks
- Define performance hardware/software interfaces. Write micro architecture and design specifications
- Define efficient micro-architecture and block partitioning/interfaces and flows
Requirements For Network Design Engineer, Google Cloud
- Bachelor's degree in BSC, or a related field, or equivalent practical experience
- 10 years of experience architecting networking ASICs from specification to production
- Experience working with design networking like: RDMA and or packet processing and system design principles
- Experience developing RTL for ASIC subsystems
- Experience in Cross-functional, micro-architecture, design, verification, logic synthesis, and timing closure
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