Senior Physical Design Engineer, Mixed Signal, Silicon

Google organizes world's information and makes it universally accessible and useful, combining AI, Software, and Hardware.
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Senior Software Engineer
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5,000+ Employees
5+ years of experience
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Description For Senior Physical Design Engineer, Mixed Signal, Silicon

Google is seeking a Senior Physical Design Engineer to join their hardware team, focusing on custom silicon solutions for direct-to-consumer products. This role combines cutting-edge hardware development with Google's innovative technology stack to create next-generation computing experiences. The position requires expertise in physical design, with emphasis on Place and Route (PnR), Static Timing Analysis (STA), and power integrity analysis.

As a Senior Physical Design Engineer, you'll work on developing custom silicon solutions that power Google's consumer products. You'll collaborate closely with front-end designers and back-end physical design integration engineers to deliver high-quality results. The role involves sophisticated technical skills in ASIC design, timing analysis, and power optimization.

The ideal candidate will have strong experience with physical design tools and methodologies, including PnR/APR, STA, EMIR, and DRC tools/flows. Knowledge of low-power design techniques and experience with advanced Engineering Change Order (ECO) techniques is highly valued. You'll be part of a diverse team that pushes boundaries and contributes to products used by millions worldwide.

This position offers the opportunity to work on cutting-edge hardware projects at one of the world's leading technology companies. You'll contribute to innovative solutions that enhance Google's hardware experiences, focusing on performance, efficiency, and integration. The role combines technical expertise with collaborative teamwork to create impactful technology solutions.

Last updated a month ago

Responsibilities For Senior Physical Design Engineer, Mixed Signal, Silicon

  • Generate high-quality Place and Route (PnR) results for digital blocks, including DRC and LVS signoff
  • Monitor timing of blocks with modern Static Timing Analysis (STA) tools and techniques
  • Analyze designs based on key metrics, including power, area, and performance trade-off
  • Apply engineering best practices to the design and implementation of ASIC blocks
  • Analyze power integrity Electromagnetic migration and IR drop (EMIR) of blocks and implement fixes

Requirements For Senior Physical Design Engineer, Mixed Signal, Silicon

Python
  • Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
  • 5 years of experience in physical design
  • Experience with PnR/APR, STA, EMIR, and DRC tools/flows working on synthesized designs
  • Experience in one or more scripting languages (e.g., Tcl, Python, etc.)

Benefits For Senior Physical Design Engineer, Mixed Signal, Silicon

Medical Insurance
Vision Insurance
Dental Insurance
Parental Leave
  • Equal employment opportunity
  • Inclusive work environment
  • Comprehensive health benefits
  • Parental leave
  • Accommodation for disabilities

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