Silicon AI/ML DFT Engineer, TPU, Google Cloud
Description For Silicon AI/ML DFT Engineer, TPU, Google Cloud
Google is seeking a Silicon AI/ML DFT Engineer to join their Technical Infrastructure team, focusing on TPU (Tensor Processing Unit) technology. This role is crucial in shaping the future of AI/ML hardware acceleration at Google Cloud. The position involves working on cutting-edge TPU technology that powers Google's most demanding AI/ML applications.
The role combines hardware design and testing expertise, specifically focusing on Design for Testing (DFT) methodologies for digital and mixed-signal chips. You'll be responsible for defining silicon test strategies, implementing DFT specifications for next-generation SoCs, and working closely with the DFT Organization. The position requires expertise in test design, verification, and post-silicon debugging.
As part of Google's Technical Infrastructure team, you'll contribute to maintaining and developing data centers and next-generation Google platforms. The team takes pride in being the engineers' engineers, focusing on keeping networks running optimally and ensuring the best user experience.
The ideal candidate should have a strong background in Electrical Engineering with experience in DFT specification and architecture. They should be familiar with EDA test tools and ASIC DFT synthesis. Additional expertise in IP integration, SoC cycles, and fault modeling would be advantageous.
This role offers the opportunity to work on innovative technology that powers products used by millions worldwide. You'll be part of a diverse team that pushes boundaries in custom silicon solutions, specifically for TPU architecture within AI/ML-driven systems. The position focuses on reducing test costs, increasing production quality, and enhancing yield in Google's critical infrastructure.
Responsibilities For Silicon AI/ML DFT Engineer, TPU, Google Cloud
- Develop DFT strategy and architecture, including hierarchical DFT/Memory Built-In Self Test (MBIST), IJTAG/TAP, and Hi-Speed IO
- Insert DFT logic, including boundary scan, scan chains, DFT Compression, Logic Built-In Self Test (BIST), Test Access Point (TAP) controller, Clock Control block, and other DFT IP blocks
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces
- Document DFT architecture and test sequences, including boot-up sequence associated with test pins
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve test quality and support post-silicon test team
Requirements For Silicon AI/ML DFT Engineer, TPU, Google Cloud
- Bachelor's degree in Electrical Engineering or a related field, or equivalent practical experience
- 3 years of experience in DFT specification definition architecture and insertion
- Experience using electronic design automation (EDA) test tools (e.g., Spyglass, Tessent)
- Experience with ASIC DFT synthesis, STA, simulation, and verification flow
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