Silicon Low Power Design Engineer, TPU, Google Cloud

Google is seeking a Silicon Low Power Design Engineer to join their TPU team within Google Cloud. This role focuses on developing cutting-edge SoCs used to accelerate machine learning computation in data centers. As part of a diverse team, you'll be responsible for pushing boundaries in custom silicon solutions that power Google's direct-to-consumer products.

The position involves solving technical problems with innovative and practical logic solutions, while evaluating design options considering complexity, performance, power, and area. You'll work closely with various teams including architecture, verification, power and performance, and physical design to deliver high-quality designs for next-generation data center accelerators.

The Technical Infrastructure team at Google is responsible for building and maintaining the architecture that keeps Google's product portfolio running. This includes developing and maintaining data centers and building next-generation Google platforms. The team takes pride in being the engineers' engineers and focuses on ensuring networks remain operational to provide users with the best and fastest experience possible.

This role requires expertise in ASIC/SoC development with a strong focus on power optimization. The ideal candidate will have experience with low power schemes, power estimation, and ASIC design verification. Knowledge of programming languages like Python, C/C++, or Perl, along with experience in SoC designs and integration flows, would be beneficial.

Google offers an inclusive work environment and is committed to building a diverse workforce. They provide equal employment opportunities regardless of background and support accommodations for applicants who need them. The position requires English proficiency to facilitate efficient global collaboration and communication.