SoC RTL Design Engineer
Description For SoC RTL Design Engineer
Google is seeking a talented SoC RTL Design Engineer to join their Devices & Services team. This role offers an exciting opportunity to work on custom silicon solutions that power Google's direct-to-consumer products. As part of a diverse team, you'll be at the forefront of innovation, developing hardware solutions that impact millions of users worldwide.
The position requires strong expertise in RTL coding, microarchitecture design, and system integration. You'll be working with cutting-edge technology, defining and implementing subsystems for SoCs, and collaborating with cross-functional teams to deliver high-quality designs. The role combines technical depth in hardware design with the opportunity to shape next-generation hardware experiences.
The ideal candidate should have a solid foundation in electrical engineering or computer science, with specific expertise in RTL coding using Verilog or SystemVerilog. Experience with STA closure, verification planning, and system-level integration is crucial. Knowledge of processor cores, interconnects, security, and power domains is highly valued.
This position offers the chance to work at one of the world's leading technology companies, contributing to products that combine the best of Google's AI, Software, and Hardware capabilities. You'll be part of a team focused on making computing faster, seamless, and more powerful for users worldwide. The role provides excellent growth opportunities and the chance to work on challenging technical problems with significant impact.
Google offers a collaborative environment, emphasizing diversity and inclusion, and provides the opportunity to work on innovative projects that push the boundaries of hardware technology. The position is based in Bengaluru, India, and requires strong communication skills and the ability to work effectively in a global team setting.
Responsibilities For SoC RTL Design Engineer
- Define the microarchitecture of Subsystems or SoCs and work with the team to deliver a quality, schedule compliant design
- Perform RTL coding for Subsystems/SoC integration, function/performance simulation debug, Lint/CDC/FV/UPF checks
- Work closely with the cross-functional team of Architecture, Verification, Design for Test, Physical Design, and Software teams to make design decisions
- Define the block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc
Requirements For SoC RTL Design Engineer
- Bachelor's degree in Electrical Engineering, Computer Science, or equivalent practical experience
- 3 years of experience in RTL coding using Verilog or Systemverilog language
- Experience in STA closure, DV test-plan review, and coverage analysis of the sub-system and chip level verification
- English proficiency is required
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