TPU Compute RTL Design Engineer

Google is seeking a TPU Compute RTL Design Engineer to join their Technical Infrastructure team. This role focuses on developing Application-specific integrated circuits (ASICs) used to accelerate computation in data centers. As part of the team developing custom silicon solutions, you'll be instrumental in powering Google's direct-to-consumer products. The position involves working on project definition, design, and implementation of next-generation data center accelerators.

The role requires expertise in digital design using SystemVerilog RTL and deep understanding of computer architecture principles. You'll collaborate with cross-functional teams including software, architecture, and validation teams to ensure optimal design implementation. The position offers competitive compensation including base salary, bonus, equity, and comprehensive benefits.

The Technical Infrastructure team is crucial in maintaining Google's vast network of data centers and platforms, ensuring users have the best and fastest experience possible. This team takes pride in being the engineers' engineers, working on cutting-edge technology that powers Google's extensive product portfolio.

This is an excellent opportunity for someone with strong technical skills in hardware design and computer architecture who wants to make a significant impact on Google's infrastructure. The role offers the chance to work on innovative technology that affects millions of users worldwide, while being part of a diverse team that pushes boundaries in hardware development.

The position comes with Google's comprehensive benefits package and the opportunity to work in either Sunnyvale, CA or Madison, WI. Google maintains a strong commitment to diversity, equality, and inclusion, fostering a culture of belonging and equal opportunity for all candidates.