Principal Logic Engineer
Description For Principal Logic Engineer
Microsoft Silicon, Cloud Hardware, and Infrastructure Engineering (SCHIE) is seeking a Principal Logic Engineer to join their team responsible for powering Microsoft's "Intelligent Cloud" mission. This role is crucial in delivering operational measures of success for hardware manufacturing, improving planning processes, quality, delivery, scale, and sustainability related to Microsoft cloud hardware.
As a Principal Logic Engineer, you will be working on high-performance Dynamic Random-Access Memory (DRAM) memory controllers and DDR4/5 PHYs. Your expertise will be instrumental in defining and delivering customer-focused solutions, providing insights, and implementing future technical solutions to manage and optimize Cloud infrastructure.
Key responsibilities include:
- Microarchitecting major blocks of DRAM Memory Controllers
- Implementing high-quality designs in Verilog RTL
- Interfacing with PHY vendors
- Collaborating with front-end and physical design teams
- Ensuring design quality in terms of functionality, timing, and various checks
The ideal candidate will have 9+ years of technical engineering experience, with a strong background in DDR4/DDR5 DRAM Memory Controller design, knowledge of JEDEC DDR5 Specifications, and proficiency in Verilog and System Verilog. Experience with high-speed digital design and familiarity with synthesis tools are also crucial.
Microsoft offers a competitive salary range of $137,600 - $267,000 per year (higher in San Francisco and New York City areas), along with excellent benefits including healthcare, educational resources, savings plans, and generous time off.
Join Microsoft's mission to empower every person and organization on the planet to achieve more. Be part of a culture that values growth, innovation, and collaboration, while working on cutting-edge technology that powers Microsoft's vast cloud infrastructure.
Responsibilities For Principal Logic Engineer
- Microarchitect major blocks of a DRAM Memory Controller and implement the design with high quality in Verilog RTL
- Interface with PHY vendor
- Work closely with front end design and physical design teams
- Implement additional required functional units in Verilog
- Ensure high quality of the design from functionality, timing, CDC, RDC, and LEC perspectives
- Embody Microsoft's Culture and Values
Requirements For Principal Logic Engineer
- 9+ years of related technical engineering experience or equivalent combination of education and experience
- 8+ years of experience with DDR4 or DDR5 DRAM Memory Controller design
- Knowledge of JEDEC DDR5 Specification
- Fluency in Verilog and System Verilog
- Experience with DRAM PHY and Interface Protocol (DFI)
- High speed digital design experience
- Ability to pass Microsoft Cloud Background Check
Benefits For Principal Logic Engineer
- Industry leading healthcare
- Educational resources
- Discounts on products and services
- Savings and investments
- Maternity and paternity leave
- Generous time away
- Giving programs
- Opportunities to network and connect
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