Senior Formal Verification Engineer
Description For Senior Formal Verification Engineer
Microsoft is seeking a Senior Formal Verification Engineer to work in the dynamic Microsoft Artificial Intelligence Silicon Engineering team (AISiE). The role involves owning formal verification of complex modules at the IP/Subsystem/SOC level, collaborating with architecture and design teams, and innovating new technologies. The ideal candidate should have 7+ years of experience in design verification with 4+ years in formal verification techniques on complex SoC IP's.
Key responsibilities include:
- Deploying advanced formal techniques and creating abstraction models for convergence
- Creating and verifying formal verification test plans
- Debugging RTL to identify failure scenarios
- Working with vendors on resolving hard design and tool problems
- Articulating formal verification coverage to partners
The role offers the opportunity to work on cutting-edge custom IP and SoC designs for Microsoft's diverse range of systems, from Xbox to Azure cloud servers. The ideal candidate should be passionate about developing world-class formal verification solutions and have strong proficiency in scripting languages like Python or Perl.
Microsoft offers a comprehensive benefits package, including industry-leading healthcare, educational resources, savings and investments, parental leave, and opportunities for networking and professional growth. The company is committed to diversity, inclusion, and empowering every person and organization to achieve more.
Responsibilities For Senior Formal Verification Engineer
- Own formal verification of complex modules at the IP/Subsystem/SOC level
- Collaborate with architecture and design teams to define formal verification scope
- Identify right strategy to prove RTL correctness using advanced formal techniques
- Create and verify formal verification test plans
- Innovate new technologies, evaluate new tools, and corroborate results
- Debug RTL to identify causes of failure scenarios
- Work with vendors on resolving hard design and tool problems
- Articulate formal verification coverage of the design to partners
Requirements For Senior Formal Verification Engineer
- 7+ years of experience in design verification with 4+ years in formal verification techniques on complex SoC IP's
- Experience with formal method or formal verification technologies and abstraction techniques
- Knowledge of interpreting hardware logic, familiarity with SV/Verilog/VHDL HDLs and assertion-based languages like SVA or PSL
- Experience using industry standard EDA formal tools for property verification and logic equivalency checks
- Strong understanding of digital design principles, Datapath architecture, and arithmetic units
- Strong proficiency in scripting languages such as Python or Perl with excellent debugging skills
Benefits For Senior Formal Verification Engineer
- Industry leading healthcare
- Educational resources
- Discounts on products and services
- Savings and investments
- Maternity and paternity leave
- Generous time away
- Giving programs
- Opportunities to network and connect
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