Senior Verification Engineer
Description For Senior Verification Engineer
Microsoft's Silicon team is seeking a Senior Verification Engineer to join their Artificial Intelligence System on Chip (AISoC) team. This role is crucial in delivering premium-quality designs for cutting-edge silicon solutions. The position involves working on diverse systems from Xbox gaming to Azure cloud servers, combining hardware engineering with AI innovation. The ideal candidate will have 7+ years of experience in design verification, with expertise in computer architecture and RTL design. The role offers a hybrid work environment with up to 50% work from home flexibility. Microsoft provides a comprehensive benefits package and promotes a culture of inclusion and innovation. The position involves working with state-of-the-art verification technologies and methodologies, making it an excellent opportunity for experienced verification engineers looking to impact the future of AI hardware development. The company's mission to empower every person and organization globally makes this role particularly meaningful for those wanting to contribute to transformative technology solutions.
Responsibilities For Senior Verification Engineer
- Plan verification of complex design IP/SoC interacting with architecture and design engineers
- Create and enhance constrained-random verification environments using SystemVerilog and UVM
- Develop tests using UVM or C/C++
- Analyse and debug test failures with designers
- Identify and write functional coverage for stimulus and corner cases
- Close coverage to plug verification holes and meet tape out requirements
Requirements For Senior Verification Engineer
- 7+ years of experience in design verification with proven track record of delivering complex CPU or SoC IP's
- In-depth knowledge of verification principles, testbenches, stimulus generation, and UVM or C++ based test environments
- Solid understanding of computer architecture
- Substantial background in debugging RTL (Verilog) designs and simulation/emulation environments
- Scripting language such as Python or Perl
- Hands on experience in Formal property verification (desirable)
- Knowledge in high-speed protocols like DDR, PCIe, Ethernet (desirable)
- Processor based testbenches and emulation (desirable)
Benefits For Senior Verification Engineer
- Industry leading healthcare
- Educational resources
- Discounts on products and services
- Savings and investments
- Maternity and paternity leave
- Generous time away
- Giving programs
- Opportunities to network and connect
Jobs Related To Microsoft Senior Verification Engineer
