CPU RTL Power Design -Staff/Sr Staf/Principal Eng

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Description For CPU RTL Power Design -Staff/Sr Staf/Principal Eng

Qualcomm is seeking a talented CPU RTL Power Design Engineer at the Staff/Sr Staff/Principal level to join their team in Bangalore. This role focuses on CPU RTL Power targeted for high performance, low power devices. The position requires extensive experience in CPU RTL power modeling and estimation, with responsibilities including power analysis, optimization, and working with cross-functional teams.

The ideal candidate will have deep expertise in CPU or ASIC low power design, including active and idle power optimization, RTL clock gating techniques, and CPU power modeling. They will be responsible for creating comprehensive power models, identifying early power targets, and achieving correlation with physical design while analyzing power/performance/area tradeoffs.

Qualcomm offers an exceptional work environment where employees can collaborate with leading engineering and technology experts in the industry. The company provides comprehensive benefits including world-class health coverage, financial planning programs, and continuous learning opportunities. This role presents an exciting opportunity to work on cutting-edge technology while contributing to world-changing innovations at a global technology leader.

The position requires strong technical skills in Verilog/VHDL, scripting languages like Python/Perl, and experience with low-power simulation tools. The successful candidate will play a crucial role in developing energy-efficient CPU designs while working in a fast-paced, dynamic environment that fosters innovation and professional growth.

Last updated 6 days ago

Responsibilities For CPU RTL Power Design -Staff/Sr Staf/Principal Eng

  • Estimate/analyze RTL power for CPU modules and optimize power
  • Create comprehensive CPU power models
  • Build scripts to automate power estimation/analysis flow
  • Analyze power/performance/area tradeoffs
  • Work with architecture, RTL, verification and physical design teams

Requirements For CPU RTL Power Design -Staff/Sr Staf/Principal Eng

Python
  • BS degree in Electrical or Computer Engineering with 15+ years of CPU RTL power modeling and estimation experience
  • Deep understanding of CPU or ASIC low power design
  • Working knowledge of Verilog and/or VHDL
  • Knowledge of logic design principles
  • Strong problem solving, organizational and communication skills

Benefits For CPU RTL Power Design -Staff/Sr Staf/Principal Eng

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
  • World-class health coverage for employees and dependents
  • Financial planning programs
  • Emotional/mental health support
  • Wellbeing programs
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship programs

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