DDR DV Principal Engineer

Leading technology innovator that pushes boundaries to enable next-generation experiences and drives digital transformation for a smarter, connected future.
Hardware
Principal Software Engineer
In-Person
4+ years of experience
Enterprise SaaS · Hardware

Description For DDR DV Principal Engineer

Qualcomm is seeking a Principal DDR-PHY Design Verification Engineer to work on next-generation System-on-chip (SoC) solutions for smartphones, tablets, and laptops. This role combines deep technical expertise in DDRPHY architecture and verification with leadership responsibilities. The ideal candidate will have extensive experience in Design Verification of complex IPs, with hands-on expertise in DDRPHY architecture, DFI protocol, and Jedec standards.

The position offers an opportunity to work with cutting-edge technology at a leading global semiconductor company. You'll be responsible for developing comprehensive test plans, managing verification environments, and ensuring quality through rigorous testing and debugging processes. The role requires collaboration with cross-functional teams including Design, Subsystem/SOC, and SVE teams.

Qualcomm offers an exceptional work environment with comprehensive benefits, including world-class health coverage, financial planning support, and professional development opportunities. The company's commitment to innovation and technological advancement makes it an ideal place for engineers looking to make a significant impact in the semiconductor industry.

This role is perfect for someone who combines technical expertise with strong leadership abilities and wants to be at the forefront of mobile technology development. You'll be working with some of the industry's brightest minds while contributing to products that impact millions of users worldwide.

Last updated 9 days ago

Responsibilities For DDR DV Principal Engineer

  • Design Verification of complex IPs
  • Ownership of DV test bench and associated collaterals
  • Develop test plan and test cases to cover design feature set
  • Debug regression signatures and identifying bug fixes
  • Quality sign-off and required documentation
  • Debug and root cause SS/SOC/post silicon issues
  • IP level /Sub-system level verification

Requirements For DDR DV Principal Engineer

Java
Python
  • Bachelor's degree in Computer Science, Electrical/Electronics Engineering or related field with 4+ years experience
  • Experience in verification and computational logic design/verification concepts
  • Expertise in Verilog/System Verilog and UVM/OVM
  • Strong debugging, Analytical and problem-solving skills
  • Experience in developing Monitors, Scoreboards, Sequencers
  • Communication and collaboration skills
  • Understanding of standard bus protocol like AHB, AXI protocols

Benefits For DDR DV Principal Engineer

Medical Insurance
Dental Insurance
Vision Insurance
Mental Health Assistance
Education Budget
  • World-class health coverage for employees and dependents
  • Financial planning and future security programs
  • Emotional/mental strength and resilience support
  • Wellbeing programs
  • Continuous learning and development programs
  • Tuition reimbursement
  • Mentorship programs

Interested in this job?

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