This is a phone screen. Introduce yourself, and proceed with three technical questions. If you pass these, there will be four rounds of panel interviews. The rest of the line is to make it 30 words minimum.
FIFO depth calculation using a 32-bit adder to add two 64-bit data. Detect every 1-bit position for a signal.
The following metrics were computed from 2 interview experiences for the AMD ASIC Design Engineer role in San Jose, California.
AMD's interview process for their ASIC Design Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for AMD's ASIC Design Engineer interview process in San Jose, California.