I applied through my university. The interview was about 1 hour long, mostly technical questions, about Verilog, timing analysis of digital logic and power dissipation. The questions weren't difficult, but the interviewer seemed strangely critical of my answers. I'm not sure if he was doing it on purpose, but he came off a little harsh.
How to reduce static and dynamic power dissipation in CMOS logic.
The following metrics were computed from 1 interview experience for the AMD CAD Department PEY role in Canada.
AMD's interview process for their CAD Department PEY roles in Canada is extremely selective, failing the vast majority of engineers.
Candidates reported having very negative feelings for AMD's CAD Department PEY interview process in Canada.