The interview was for a role in the CPU Performance modeling team. The team's responsibilities include simulating new features in architectural simulators, correlation with RTL, and post-silicon performance validation.

The interview consisted of three rounds. Two rounds were related to computer architecture, and one was for coding and DSA.

Some of the questions were as follows:

1. How do you classify a workload as CPU-intensive or memory-intensive (with and without altering the CPU microarchitecture)?
2. Explain a branch predictor. What is one major difference between ARM and x86 CPU branch predictors?
3. What is the need for architecture simulators? Why not simulate workloads in RTL directly?
4. Given a multicore system with a fixed memory architecture, how does single-core performance vary with scheduling identical single-threaded workloads on increasing cores?
5. What are some pipeline hazards? How do you overcome them?

The coding round consisted of questions about OOPS in C++ and some LeetCode medium-level DSA questions.