I was referred and was reached out to within 3 days.
The interview consisted of generic behavioral questions and some technical questions.
I was applying for an entry-level position.
My advice: please try to get an internship in DV or ask for projects in DV at school.
An arbiter with an asynchronous reset receives four request signals, R1, R2, R3, and R4, and generates four grant signals, G1, G2, G3, and G4. Request R1 has the highest priority, and request R4 has the lowest priority.
Draw the state diagram.
Draw a count-to-5 counter logic circuit.
Generate a 2GHz clock and code the FSM (the one with the asynchronous reset) in Verilog.
The following metrics were computed from 2 interview experiences for the AMD Design Verification Engineer role in Austin, Texas.
AMD's interview process for their Design Verification Engineer roles in Austin, Texas is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for AMD's Design Verification Engineer interview process in Austin, Texas.