Questions covered FSM, the difference between SystemVerilog and Verilog, and coverage concepts. There were five interviews, and the process was very repetitive. I was asked to go over my resume and work experience five times, with the same questions being asked each time.
For one of the interviews, the interviewer read my resume for almost an hour while I waited. In another interview, the interviewer was mumbling and using many abbreviations.
It was an okay experience, but perhaps they need to be more organized.
Design an FSM for an elevator.
Describe different kinds of coverage.
Describe some RTL bugs you found in your current role.
Describe a UVM testbench.
Explain how sequences and drivers are connected.
The following metrics were computed from 3 interview experiences for the AMD Design Verification Engineer role in Boxborough, Massachusetts.
AMD's interview process for their Design Verification Engineer roles in Boxborough, Massachusetts is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having mixed feelings for AMD's Design Verification Engineer interview process in Boxborough, Massachusetts.