Good Projects.
Always driven to new things. Open to junior engineers also. Good work-life balance.
Financial condition draining some good talent.
Internal politics.
BU driven.
There were a total of 6 rounds of interviews, starting with SystemVerilog, UVM, projects, analytical, and SOC level. I did not find it very difficult. The analytical questions were tricky, but enough time was given to answer each.
The first round was a 1-hour screening test, comprising six sections. Of these, any four could be chosen. However, the Digital Design and Logical Reasoning sections were compulsory. The screening was followed by an interview. The interviewers mostly
The interviewer asked for very detailed knowledge and looked for specific keywords in the answers.
There were a total of 6 rounds of interviews, starting with SystemVerilog, UVM, projects, analytical, and SOC level. I did not find it very difficult. The analytical questions were tricky, but enough time was given to answer each.
The first round was a 1-hour screening test, comprising six sections. Of these, any four could be chosen. However, the Digital Design and Logical Reasoning sections were compulsory. The screening was followed by an interview. The interviewers mostly
The interviewer asked for very detailed knowledge and looked for specific keywords in the answers.