The recruiter called first. Then, he arranged a 45-minute phone screen in the same week. The interview questions were basic SystemVerilog and UVM related. We also talked about my previous working experiences with two other companies and research experiences from school. In the end, I didn't pass the interview because they didn't think I was a good fit.
I don't think the questions are difficult. Some coding-related questions I didn't answer well, mainly because my past experiences focused more on hardware design, not software coding.
The following metrics were computed from 2 interview experiences for the Apple ASIC Verification Engineer role in United States.
Apple's interview process for their ASIC Verification Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Apple's ASIC Verification Engineer interview process in United States.