Easy. Only about relevant projects and work experience. How to verify many design scenarios? Given one piece of RTL code, find the issues with it.
Comp architecture, aptitude, Verilog, SystemVerilog, ASIC verification.
Do you have any other offers in hand?
The following metrics were computed from 2 interview experiences for the Apple Design Verification role in Austin, Texas.
Apple's interview process for their Design Verification roles in Austin, Texas is extremely selective, failing the vast majority of engineers.
Candidates reported having very negative feelings for Apple's Design Verification interview process in Austin, Texas.