First, asking about the tool experience; asking about UVM knowledge like how and when to connect the sequencer and driver and what is their handshake; how do you deal with CDC problems; how to do the STA analysis; then finally having a coding question.
Implementation of driver class based on the figure they gave.
The following metrics were computed from 3 interview experiences for the Apple Design Verification Engineer role in San Jose, California.
Apple's interview process for their Design Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Apple's Design Verification Engineer interview process in San Jose, California.