Some one gave me referral and a recruiter contacted me. It took around 3 weeks to go onsite. Two phone interviews with managers and then onsite. Phone interviews were mainly about prior job experience, but also covers some SystemVerilog basics, like the concept of semaphore, difference between fork join, join_none and join_any, etc. Onsite interview was not quite tough. I could answer most of the questions except one interviewer. When he asked me to reverse a linked list, maybe I was too tired after a couple of interviews, but I couldn't answer that. It was a quite common interview question, and I should be able to answer that.
Reverse a linked list.
The following metrics were computed from 58 interview experiences for the Apple Design Verification Engineer role in United States.
Apple's interview process for their Design Verification Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Apple's Design Verification Engineer interview process in United States.