Taro Logo

Physical Synthesis CAD Engineer Interview Experience - Cupertino, California

April 1, 2017
Neutral ExperienceNo Offer

Process

An initial HR interview was conducted over the phone.

Next, the hiring manager contacted me for a one-hour technical phone interview.

A couple of days later, I had another one-hour technical phone interview with a different team member.

Finally, I was invited for an onsite interview. This involved eight panel members, with each person conducting a 45-minute one-on-one interview.

Questions

STA (Static Timing Analysis) Synthesis Flow Verilog code for divide-by-3 clock Basic data structures Placement and routing algorithms Transistor models Equations of current in saturation mode Low-power techniques Some behavioral questions.

Was this helpful?

Interview Statistics

The following metrics were computed from 1 interview experience for the Apple Physical Synthesis CAD Engineer role in Cupertino, California.

Success Rate

0%
Pass Rate

Apple's interview process for their Physical Synthesis CAD Engineer roles in Cupertino, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive0%
Neutral100%
Negative0%

Candidates reported having mixed feelings for Apple's Physical Synthesis CAD Engineer interview process in Cupertino, California.

Apple Work Experiences