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Senior ASIC Verification Engineer Interview Experience - United States

September 1, 2019
Positive ExperienceGot Offer

Process

A. Recruiter sent an email asking if I was interested. B. Scheduled a phone interview. C. A 50-minute phone screen interview first (just talks). D. Asked for an onsite interview on the same day. E. Followed by an onsite interview for 5 hours, which contained 5 1:1 sessions, including lunch.

Questions

  1. Discuss your work experiences and skills.
  2. Mention two substantial technical challenges or great achievements and how you resolved them.
  3. What is a singleton, how do you create one, and what are examples in UVM?
  4. A 10-stage CPU pipeline each with a delay of 10 ns. How long does it take to run 100 instructions?
  5. Write C code to determine if the machine is big-endian or little-endian.
  6. A test failed, and the designer asked you to change something to get the test working. You made the change, and the test case passed. Can you elaborate on this, mentioning what the issue was and how to fix it?
  7. You have numbers from 1 to 100 put into an array, but the array length was less than 100, so a number is missing. The array is shuffled and not sorted. Sketch an algorithm to find that number and mention its Big-O for performance and capacity.
  8. You have an unsorted array and want to find 3 elements in the array whose sum equals a specific number.
  9. Write Verilog code for a posedge/negedge detector.
  10. Deep SystemVerilog Assertions questions.
  11. Deep UVM questions (monitors with multiple analysis port connections to scoreboard, how to collect input stimuli from the DUT (via monitor or sequence/sequencer), difference between p_sequencer/m_sequencer, UVM vertical and horizontal reuse, write code for a TRANSLATION sequence, how to enable UVM acceleration in Emulation, etc.).
  12. Deep SystemVerilog constrained random questions.
  13. Deep code optimizations, performance, and capacity questions.
  14. Deep Emulation questions.
  15. Verify an arbiter using assertions.
  16. Sketch an algorithm to find the Kth greatest element of an unsorted array. What is the Big-O notation?
  17. Write code to rotate a matrix. What is the Big-O notation?
  18. Power and clock optimizations questions.
  19. Deep verification questions.
  20. UVM Register Layer very deep questions.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Apple Senior ASIC Verification Engineer role in United States.

Success Rate

0%
Pass Rate

Apple's interview process for their Senior ASIC Verification Engineer roles in the United States is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Apple's Senior ASIC Verification Engineer interview process in United States.

Apple Work Experiences