One telephonic interview.
One full-day interview at Apple, Cupertino.
Five people interviewed for 45 minutes each.
The third person, who was a manager, took me to the cafeteria for lunch.
Interviewers were friendly, and the questions were very technical. Though the position was for NCG, I was interviewed intensely because of my past experience in the field.
Few questions on writing constraints for certain scenarios.
FSM for number divisible by 3.
UVM subscriber, sequences, TLM ports, and FIFO.
Write code for random number generation for a given distribution and ranges.
Byte addressing in an integer memory system.
Constrain for non-overlapping segment addresses generation.
Explain any testbench architecture you have worked on.
Lots of simple questions to test SystemVerilog and OOP concepts.
The following metrics were computed from 3 interview experiences for the Apple SoC Verification Engineer role in Cupertino, California.
Apple's interview process for their SoC Verification Engineer roles in Cupertino, California is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Apple's SoC Verification Engineer interview process in Cupertino, California.