The first round was taken by a lead engineer. I was first asked briefly about my previous experience and my current studies.

The interviewer then asked me about verification tools, VHDL, Verilog and UVM.

The interview was very straight forward, however, I was not much prepared in the verification domain and therefore could not deliver the questions as per the expectation. This, however, helped me understand where I am lacking and I now know where to focus my attention.

Overall, I had a good experience. I am glad I was selected for the first round.

How do you write a test bench for decoder and ensure all slaves are receiving the correct output?

There was a coding problem to check if we are receiving inverted clock output.