During the interview we mainly talked about creating verification environments using UVM. Additionally there were some tricky algorithm questions in System Verilog.
There were also some random questions about computer architecture, like cache coherency.
Basic UVM questions, advanced SystemVerilog
The following metrics were computed from 5 interview experiences for the Arm Verification Engineer role in United Kingdom.
Arm's interview process for their Verification Engineer roles in the United Kingdom is very selective, failing most engineers who go through it.
Candidates reported having very good feelings for Arm's Verification Engineer interview process in United Kingdom.