I have been exposed to two rounds of interviewing, including one 30-minute chat regarding more general questions about my experience, as well as about their team. The second interview was a technical round with two engineers via a coding platform. The questions covered hardware questions, design, and random constraint verification in SystemVerilog, as well as software questions in which I was asked to develop an algorithm in a software language of my choice.
Implement a 4-bit counter in SV.
The following metrics were computed from 1 interview experience for the Astera Labs Design Verification Engineer role in Toronto, Canada.
Astera Labs's interview process for their Design Verification Engineer roles in Toronto, Canada is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Astera Labs's Design Verification Engineer interview process in Toronto, Canada.