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ASIC Design Engineer Interview Experience - Irvine, California

June 1, 2012
Positive ExperienceGot Offer

Process

The phone interview was normal, with questions about projects on the resume.

I was called on-site two weeks later. The questions were:

  • Divide by 2 clock
  • Divide by 3 clock
  • FIFO read/write rates for equilibrium
  • 3-bit Gray code counter
  • Low power techniques
  • Parallel processing

Questions

What is the relationship between read and write clocks for different data widths in a FIFO?

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Broadcom ASIC Design Engineer role in Irvine, California.

Success Rate

0%
Pass Rate

Broadcom's interview process for their ASIC Design Engineer roles in Irvine, California is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive50%
Neutral0%
Negative50%

Candidates reported having mixed feelings for Broadcom's ASIC Design Engineer interview process in Irvine, California.

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