Behavioral questions (about experiences, also asked for review of code that I made), random digital logic questions (half adder, full adder, etc.), then variety of SystemVerilog coding questions. Also asked a couple of C questions.
Difference between half and full adder.
The following metrics were computed from 1 interview experience for the ByteDance ASIC Design Engineer role in United States.
ByteDance's interview process for their ASIC Design Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for ByteDance's ASIC Design Engineer interview process in United States.