I was contacted by HR to set up an interview call. And later, I was in contact with the manager of the Verification Team to finalize the interview timings. The interview was a Skype call for about an hour and the decision was made in the next 8-10 days.
Initially the questions were based on my resume. Later some concepts of Verilog, like blocking-non blocking assignments, were discussed. He asked me to write a small Verilog code also.
The following metrics were computed from 1 interview experience for the Cadence Design Systems Hardware Emulation and Verification role in Austin, Texas.
Cadence Design Systems's interview process for their Hardware Emulation and Verification roles in Austin, Texas is extremely selective, failing the vast majority of engineers.
Candidates reported having mixed feelings for Cadence Design Systems's Hardware Emulation and Verification interview process in Austin, Texas.