Senior Verification Engineer Interview Experience - San Jose, California
Process
Contacted by HR thru LinkedIn. Set up a short HR discussion followed by a phone interview.
Technical phone interview: General resume questions were asked. Experience. OVM/UVM basic questions. How will you tell the size of an array without using the foreach construct of SystemVerilog? MESI/MOSI.
A small team was looking for a senior person. So not selected
Questions
There was nothing specific.
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Interview Statistics
The following metrics were computed from 1 interview experience for the Cadence Design Systems Senior Verification Engineer role in San Jose, California.
Success Rate
Cadence Design Systems's interview process for their Senior Verification Engineer roles in San Jose, California is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having mixed feelings for Cadence Design Systems's Senior Verification Engineer interview process in San Jose, California.
Cadence Design Systems Work Experiences
- 5.0Culture amazingLead Engineer • Current EmployeeSan Jose, CaliforniaAugust 19, 2023Pros: Nice place good growth excellent cultureCons: There are less RSUs in the company.
- 5.0Good space to retireSenior Applications Engineer • Current EmployeeSan Jose, CaliforniaOctober 23, 2025Pros: Job security, no unnecessary spending at the companyCons: Might give lower salary, growth could be slow
- 3.0Drudgery, good moneySenior Software Engineering Manager • Former EmployeeSan Jose, CaliforniaOctober 22, 2015Pros: - With Lip Bu Tan he knows how to keep share holders happy. The company is going up in value. - You can get by with ~45 hours a week of work, which is unusual for the Bay Area.Cons: Older than average workforce. If you're a young engineer, you'll be the youngest person probably. This is good as you get to hangout with experienced people. But don't expect a social life from your workplace.
