Timing Analysis Engineer Interview Experience
Process
I got 2 phone screen in consequence 2 weeks(2012 Jan), but I didn't do very well, so no further contact till now.
He ask about STA flow and some basic FlipFlop and Latch issue and set up/hold time and some concept of C++ when implement a graph.
It's a timing analysis group and the interviewer is the group leader.
In conclude, this kind of group will focus on graph algorithm like DFS and coding ability like C++ and of course some digital design concept like I mention above.
Hope it help!
Questions
What kind of data structure should we use to implement a graph in C++?
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Interview Statistics
The following metrics were computed from 1 interview experience for the Cadence Design Systems Timing Analysis Engineer role.
Success Rate
Cadence Design Systems's interview process for their Timing Analysis Engineer roles is extremely selective, failing the vast majority of engineers.
Experience Rating
Candidates reported having mixed feelings for Cadence Design Systems's Timing Analysis Engineer interview process.
Cadence Design Systems Work Experiences
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