The whole selection and recruitment process took more than a month. It was a seamless experience. A written test followed by Technical and HR rounds were conducted. The interview was fully relevant to the electronics and VLSI domain.

1. Difference between inter-assignment and intra-assignment delay.

2. Blocking and non-blocking procedural blocks.

3. How to design an AND gate using a MUX.

4. Signals used in a FIFO.

5. Does a FIFO require an address or not?

6. What do you understand by synchronous and asynchronous circuits?

7. How can we disable randomization?

8. Why do we use virtual interfaces in a verification environment?

9. How to select and provide a particular test case that was generated in a generator block?