Referred by a friend, I received a call from the recruiter a few days later. I had a phone interview and was later called upon for an onsite interview. I was asked to code digital logic in Verilog in a shared Google Doc.

Implement a hardware-based LRU scheme for a 4-way set-associative cache.

Based on the critical path, find the maximum frequency of operation (considering combinational logic delays, flip-flop delays, flip-flop setup times, and clock skew).

Detect when N numbers have arrived, based on a control signal. Flag the average of all N numbers once they have arrived.

Async FIFO sizing. Throughput of putting data every clock cycle. Both read and write clocks are the same speed.