Had 4 rounds (2 technical, 1 behavioral, 1 technical).
Being strong in SystemVerilog fundamentals should help you out.
Coding questions are tricky, testing knowledge on multiple concepts of SV and UVM.
About UVM phases and how I use them.
The following metrics were computed from 2 interview experiences for the Google ASIC Design Verification Engineer role in Sunnyvale, California.
Google's interview process for their ASIC Design Verification Engineer roles in Sunnyvale, California is fairly selective, failing a large portion of engineers who go through it.
Candidates reported having very good feelings for Google's ASIC Design Verification Engineer interview process in Sunnyvale, California.