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ASIC Design Verification Engineer Interview Experience - Sunnyvale, California

November 1, 2024
Positive ExperienceNo Offer

Process

Had 4 rounds (2 technical, 1 behavioral, 1 technical).

Being strong in SystemVerilog fundamentals should help you out.

Coding questions are tricky, testing knowledge on multiple concepts of SV and UVM.

Questions

About UVM phases and how I use them.

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Google ASIC Design Verification Engineer role in Sunnyvale, California.

Success Rate

50%
Pass Rate

Google's interview process for their ASIC Design Verification Engineer roles in Sunnyvale, California is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive50%
Neutral50%
Negative0%

Candidates reported having very good feelings for Google's ASIC Design Verification Engineer interview process in Sunnyvale, California.

Google Work Experiences