It was quite challenging. They even asked several UVM-related concepts, including:
These were asked to assess understanding of verification methodology at a beginner level. SV concepts need to be solid.
Gave a standard FIFO design and told me to explain how I'll write a testbench for that.
The following metrics were computed from 1 interview experience for the Google ASIC Engineer role in India.
Google's interview process for their ASIC Engineer roles in India is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Google's ASIC Engineer interview process in India.