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ASIC Engineer Interview Experience - India

February 1, 2025
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Process

It was quite challenging. They even asked several UVM-related concepts, including:

  • Basic testbench structure
  • Sequence generation
  • Configuration mechanisms

These were asked to assess understanding of verification methodology at a beginner level. SV concepts need to be solid.

Questions

Gave a standard FIFO design and told me to explain how I'll write a testbench for that.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Google ASIC Engineer role in India.

Success Rate

0%
Pass Rate

Google's interview process for their ASIC Engineer roles in India is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Google's ASIC Engineer interview process in India.

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