Round 0 – Resume Screening: I optimized my resume using ATS tools like ResumeWorded, aligning keywords with the job description and quantifying impact (e.g., “Improved functional coverage by 30% using constraint randomization”).

Round 1 – SystemVerilog Fundamentals: Covered arrays, IPC, fork-join, OOP (inheritance, polymorphism), constraints (weighted, implication), and assertions. Emphasis was on explaining concepts clearly and debugging edge cases.

Round 2 – UVM Concepts: Focused on class hierarchy, factory methods, config_db vs resource_db, and RAL integration. I demonstrated how I build modular, reusable testbenches using UVM phases and configuration techniques.

Round 3 – Problem Solving & Debugging: Included designing and verifying FIFO and protocol-based modules. I debugged failing simulations using waveform analysis and refined coverage goals using targeted sequences.

How would you debug a failing simulation where coverage is not met?