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Hardware and Verification Engineer Interview Experience - Costa Rica

August 15, 2018
Positive ExperienceNo Offer

Process

A first interview with the hiring manager, an excellent person. He asked me some questions about my resume and experience with my university projects using HDL and FPGAs.

Then, a technical interview with three engineers who were very collaborative and disposed to help. I have no complaints with them.

Questions

Questions related to finding a bug in the execution of little code using mnemonics, HDL structure for a state machine, and HDL-related questions, and OOP-related questions and identifying examples in code.

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Interview Statistics

The following metrics were computed from 1 interview experience for the Hewlett Packard Enterprise Hardware and Verification Engineer role in Costa Rica.

Success Rate

0%
Pass Rate

Hewlett Packard Enterprise's interview process for their Hardware and Verification Engineer roles in Costa Rica is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive100%
Neutral0%
Negative0%

Candidates reported having very good feelings for Hewlett Packard Enterprise's Hardware and Verification Engineer interview process in Costa Rica.

Hewlett Packard Enterprise Work Experiences