They had a technical screening first, which involved implementing a real-life trading problem with SystemVerilog. 120 minutes were given to that.
It's a basic sequential problem, and I was given a technical interview with an engineer afterward. He asked about tradeoffs if the problem had different constraints, such as if 100 more sequences were added, how would that affect my solution, etc.
If the constant that we need to compare is increased from 6 to 100, then what happens with your machine?
How would you fix it? What would you do?
How would you implement it in Verilog without using so much time on coding?
The following metrics were computed from 2 interview experiences for the IMC Trading Hardware Engineering role in United States.
IMC Trading's interview process for their Hardware Engineering roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for IMC Trading's Hardware Engineering interview process in United States.