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ASIC Design Engineer Interview Experience - United States

January 29, 2018
Positive ExperienceNo Offer

Process

The hiring manager called for a phone interview and I was invited to an on-site interview the following week. This involved a 6-hour on-site technical interview with engineers and managers. They mainly asked about FIFO, although I have a different design background.

Questions

FIFO, clock gating, latches

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Interview Statistics

The following metrics were computed from 5 interview experiences for the Intel ASIC Design Engineer role in United States.

Success Rate

0%
Pass Rate

Intel's interview process for their ASIC Design Engineer roles in the United States is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive40%
Neutral60%
Negative0%

Candidates reported having very good feelings for Intel's ASIC Design Engineer interview process in United States.

Intel Work Experiences