The hiring manager called for a phone interview and I was invited to an on-site interview the following week. This involved a 6-hour on-site technical interview with engineers and managers. They mainly asked about FIFO, although I have a different design background.
FIFO, clock gating, latches
The following metrics were computed from 5 interview experiences for the Intel ASIC Design Engineer role in United States.
Intel's interview process for their ASIC Design Engineer roles in the United States is extremely selective, failing the vast majority of engineers.
Candidates reported having very good feelings for Intel's ASIC Design Engineer interview process in United States.