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ASIC Design Engineer Interview Experience - Vancouver, British Columbia

January 1, 2020
Negative ExperienceNo Offer

Process

Sent resumé and cover letter via school co-op program. Got an email from co-op to meet at the office down by Marine-Gateway. There will be two interviewers and a bunch of questions about cover letter and resumé.

Questions

How to make an AND gate with only XOR gates.

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Intel ASIC Design Engineer role in Vancouver, British Columbia.

Success Rate

50%
Pass Rate

Intel's interview process for their ASIC Design Engineer roles in Vancouver, British Columbia is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive50%
Neutral0%
Negative50%

Candidates reported having mixed feelings for Intel's ASIC Design Engineer interview process in Vancouver, British Columbia.

Intel Work Experiences