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ASIC Design Engineer Interview Experience - Vancouver, British Columbia

May 1, 2019
Positive ExperienceGot Offer

Process

It was a 2-on-1 interview where they mostly asked about basic language knowledge in object-oriented languages. Questions were based on whether you knew the terminology or not.

Questions

How do you access a private variable in a public class from another class in Java?

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Interview Statistics

The following metrics were computed from 2 interview experiences for the Intel ASIC Design Engineer role in Vancouver, British Columbia.

Success Rate

50%
Pass Rate

Intel's interview process for their ASIC Design Engineer roles in Vancouver, British Columbia is fairly selective, failing a large portion of engineers who go through it.

Experience Rating

Positive50%
Neutral0%
Negative50%

Candidates reported having mixed feelings for Intel's ASIC Design Engineer interview process in Vancouver, British Columbia.

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