I interviewed for two positions: "ASIC Development Co-op" and "ASIC Hardware Performance Modelling Co-op". I received an offer for the latter (Performance Modelling) but not for ASIC Development, so your mileage may vary.
Both interviews took place on Cisco Webex and critically utilized its "Share Screen" feature. I recommend using some form of digital drawing tool. I used an iPad and Apple Pencil synced to OneNote, then opened OneNote on my laptop and shared that window.
Both interviews were similar and lasted around 80 minutes, though with different technical questions. There were two interviewers: one who would be your direct supervisor, and the other being your supervisor's supervisor.
Initially, they spent a good 20 minutes explaining what they do at Intel, and more importantly, at their particular group within Intel. (For those unfamiliar, Intel is internally split into operating groups, each with a specific focus.) I was interviewing for the NSG (Non-Volatile-Memory Solutions Group), so much of what was explained pertained to their work on Intel's SSDs and Optane memory.
I was grilled extensively on the single CompEng project on my resume. (I am a CS major, and the rest of my resume was tailored towards securing an SWE job.) This project involved designing a MIPS CPU from scratch in Verilog. The interviewer wanted a detailed explanation of how the CPU would execute instructions (specifically, the datapath/FSM) and the process of its implementation. This segment took approximately 30-40 minutes for both interviews.
The final portion consisted of technical questions, often referred to as "whiteboarding." The questions are listed below. While they weren't difficult by any means, the clear focus was to assess your problem-solving approach. I recommend articulating your thought process. Most importantly, avoid random "hail mary" guesses. Admit it if you don't know; they can discern it. Pseudocode is acceptable, as they don't expect anything to compile.
My interviewer mentioned he was particularly impressed that I approached the "100 primes" question by using a function call that I implemented afterward. This segregated the logic into nicely readable chunks.
Overall, I felt a significant portion of the interview was dedicated to evaluating your soft skills alongside your hard skills. This involved assessing your ability to clearly articulate complex technical subjects by breaking them down into comprehensible parts. You do need to know your material (Data Structures/Algorithms, Verilog, topics on your resume), but I felt they were more interested in whether you truly understood your own answers than anything else. There's no need to grind LeetCode extensively.
Verbal: Why can it make sense to use a tree instead of a list?
Draw: Make a NOT gate using only NAND gate(s).
Write Code: Count the number of ones in a bitstring. (Allowed to use HDL logic e.g. bit[0]==1)
Write Code: Print the first 100 primes.
The following metrics were computed from 1 interview experience for the Intel ASIC Engineer Intern role in Vancouver, British Columbia.
Intel's interview process for their ASIC Engineer Intern roles in Vancouver, British Columbia is incredibly easy as the vast majority of engineers get an offer after going through it.
Candidates reported having very good feelings for Intel's ASIC Engineer Intern interview process in Vancouver, British Columbia.