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Component Debug Engineer Interview Experience - Austin, Texas

March 1, 2016
Neutral ExperienceNo Offer

Process

Had a 30-minute phone screening/interview. I assumed there were supposed to be 10 questions answered, but only got halfway through before time was up. I was expecting hard questions about analog and digital design but was asked about simple digital logic.

Questions

Output of a NAND Gate

Using DeMorgan's Theorem, convert one design to another.

How do you design ... using NANDs only?

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Interview Statistics

The following metrics were computed from 3 interview experiences for the Intel Component Debug Engineer role in Austin, Texas.

Success Rate

0%
Pass Rate

Intel's interview process for their Component Debug Engineer roles in Austin, Texas is extremely selective, failing the vast majority of engineers.

Experience Rating

Positive33%
Neutral33%
Negative33%

Candidates reported having mixed feelings for Intel's Component Debug Engineer interview process in Austin, Texas.

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