CPU Design Verification Intern Interview Experience - College Station, Texas
Process
1 screening followed by 3 technical rounds. The screening touched on Comp arch, digital design, C programming, and assembly x86. The technical rounds focused on more Comp arch questions and digital logic design.
Questions
Design a circuit that takes 4-bit BCD as input and has the input times 5 as output.
32Kb cache, 2-way associative, and 64B line. What is the cache state and line state according to MESI when:
- Read 0x010F30
- Write 0x880F00
- Write 0x010F20
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Interview Statistics
The following metrics were computed from 1 interview experience for the Intel CPU Design Verification Intern role in College Station, Texas.
Success Rate
Intel's interview process for their CPU Design Verification Intern roles in College Station, Texas is incredibly easy as the vast majority of engineers get an offer after going through it.
Experience Rating
Candidates reported having very good feelings for Intel's CPU Design Verification Intern interview process in College Station, Texas.
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Intel Interview Questions
